Journals and Conference Publications
1. Flavia Princess Nesamani, I, J.Kanaka deva Princy , K.MariaPriyadharshini&Dr.V.LakshmiPrabha, “An Architectural Framework for Power Performance Tuning”, CIIT International Journal of Programmable Device Circuits and Systems, Vol.3 & No.2, February 2011, pp.86-90.
2. Flavia Princess Nesamani, I, K.MariaPriyadharshini, J.Kanaka deva Princy&Dr.V.LakshmiPrabha, “A Novel Optimization Technique for Multi Domain Clock Skew Scheduling”, CIIT International Journal of Programmable Device Circuits and Systems, Vol.3 & No.2, February 2011,pp.81-85.
3. K. Mariya Priyadarshini , K.Gnana Deepika,K.David Solomon Raju , “sleepy keeper approach for power performance tuning in VLSI design”, International Journal of Electronics and Communication Engineering (IJECE- 2013) ISSN 0974-2166 Volume 6, Number 1 (2013), pp. 17-28
4. K Mariya Priyadarshini, Ch,Sreedhar, “Low Power and Reduce Area Dual Edge Pulse Triggered Flip-Flop Based on Signal Feed-Through Scheme”International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), Volume 3, Issue11, November 2014.
5. K. Mariya Priyadarshini, N.V.N Ravikiran, N. Tejasri, T.C Venkat Anish, “Design Of Area And Speed Efficient Square Root Carry Select Adder Using Fast Adders”International journal of scientific and Technical Research(IJSTR), volume 3,Issue 6, June 2014.
6. K.Mariya Priyadarshini , V.Kailash, , M.Abhinaya, K.Prashanthi, Y.Kannaji, “Low Power State Retention Technique for Low Power VLSI design” International Journal of Advanced Computer Research (IJACR), (ISSN (print): 2249-7277 ISSN (online): 2277-7970), Volume-4 Number-2 Issue-15 June-2014.
7. K. Mariya Priyadarshini, M. Naga Sabari, “Comparative Analysis of a Low Power and High Speed Hybrid 1-Bit Full Adder for ULSI Circuits” International Journal of Science and Research (IJSR), ISSN (Online): 2319-7064, Volume 5 Issue 9, September 2016.
8. K Mariya Priyadarshini, Dr.R.S.Ernest Ravindran, “Novel Two Fold Edge Activated Memory Cell with Low Power Dissipation and High Speed”, International Journal of Recent Technology and EngineeringVolume 8, Issue 1, May 2019, Pages 1491-1495.
9. K Mariya Priyadarshini, Dr.R.S.Ernest Ravindran, P. Ratna Bhaskar, “A Detailed Scrutiny and Reasoning on VLSI Binary
Adder Circuits and Architectures”International Journal of Innovative Technology and Exploring EngineeringVolume 8, Issue 7, May 2019, Pages 887-895
11. D Naveen Sai , Surya Kranth G, Paradhasaradhi D, R.S Ernest Ravindran, Lakshmana Kumar M, K Mariya Priyadarshini, Five Input Multilayer Full Adder by QCA Designer” 3rd International Conference on Advances in Computing and Data Sciences, ICACDS 2019; Ghazibad India, 12 April 2019 through 13 April 2019”
12. R.S. Ernest Ravindran, Mariya Priyadarshini, Kavuri Mahesh, Vanga Krishna Vamsi , Chaitanya Eswar , Bishan Yasaswi,” A Novel 24T Conventional adder vs Low Power Reconstructable Transistor Level Conventional Adder”, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249-8958, Volume-8 Issue-5, June 2019, Pages 398-402.
13. K.Mariya Priyadarshini, Sampad Kumar Panda, R.S. Ernest Ravindran, S Sarvani, P Mohan Vinay, B Suresh Gopi Chand”Performance Analysis of Dual Edge Triggered Memory Cells using Multiple C-Elements” International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8 Issue-4, November 2019.
14. K.Mariya Priyadarshini , Vipul Agarwal , R.S. Ernest Ravindran , T.Hareesh , B.Harsha , G.V. Kalayan “Design of Low-Power, Area Efficient 2-4 and 4-16 Mixed-Logic Line Decoders” Jour of Adv Research in Dynamical & Control Systems, Vol. 11, Special Issue-08, 2019.
15. K.Mariya Priyadarshini, T.P.S. Kumar Kusumanchi, R.S. Ernest Ravindran, E.Naga Lakshmi bhavani, K.Lahari, P.Maheswari “Low Power High Speed Robust SRAM Cells” International Journal of Advanced Science and Technology Vol. 28, No. 20, (2019), pp. 53-62.
16. R. S Ernest Ravindran , K. Mariya Priyadarshini , A. Thanusha sai , P. Shiny, Sk. Sabeena “Design of Finite field Multiplier for Efficient Data Encryption” International Journal of Advanced Science and Technology Vol. 28, No. 20, (2019), pp. 42-52.
17. K. Mariya Priyadarshini , R. S. Ernest Ravindran , M. Atindra Chandra Sekhar , P. J. V. Sai Kalyan , G. Rahul “A High-Speed Precision-Controllable Approximate 16 bit Multiplier” International Journal of Advanced Science and Technology Vol. 28, No. 20, (2019), pp. 31-41
18. K. Mariya Priyadarshini,Vipul Agarwal, R. S Ernest Ravindran, K. Mercy Romitha, Pritika Kanchan, Kurra Harshita“Logical Fault Modelling Algorithm for Stuck-at-fault”, International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8 Issue-5, January 2020.
19. Priyadarshini, K.M., Ernest Ravindran, R.S., Kumar, R.V., ...Sai Bhattar, S.S., Pavan Sri Kalian, T. “Design and implementation of dual edge triggered shift registers for iot applications”, International Journal of Scientific and Technology Research, 2019, 8(10), pp. 3585–3594
20. K Mariya Priyadarshini , R.S Ernest Ravindran , Ipseeta Nanda “A Novel Two Level Edge Activated Carry Save Adder for High Speed Processors” (IJACSA) International Journal of Advance d Computer Science and Applications, Vol. 11, No. 4, May 2020.
2. Flavia Princess Nesamani, I, K.MariaPriyadharshini, J.Kanaka deva Princy&Dr.V.LakshmiPrabha, “A Novel Optimization Technique for Multi Domain Clock Skew Scheduling”, CIIT International Journal of Programmable Device Circuits and Systems, Vol.3 & No.2, February 2011,pp.81-85.
3. K. Mariya Priyadarshini , K.Gnana Deepika,K.David Solomon Raju , “sleepy keeper approach for power performance tuning in VLSI design”, International Journal of Electronics and Communication Engineering (IJECE- 2013) ISSN 0974-2166 Volume 6, Number 1 (2013), pp. 17-28
4. K Mariya Priyadarshini, Ch,Sreedhar, “Low Power and Reduce Area Dual Edge Pulse Triggered Flip-Flop Based on Signal Feed-Through Scheme”International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), Volume 3, Issue11, November 2014.
5. K. Mariya Priyadarshini, N.V.N Ravikiran, N. Tejasri, T.C Venkat Anish, “Design Of Area And Speed Efficient Square Root Carry Select Adder Using Fast Adders”International journal of scientific and Technical Research(IJSTR), volume 3,Issue 6, June 2014.
6. K.Mariya Priyadarshini , V.Kailash, , M.Abhinaya, K.Prashanthi, Y.Kannaji, “Low Power State Retention Technique for Low Power VLSI design” International Journal of Advanced Computer Research (IJACR), (ISSN (print): 2249-7277 ISSN (online): 2277-7970), Volume-4 Number-2 Issue-15 June-2014.
7. K. Mariya Priyadarshini, M. Naga Sabari, “Comparative Analysis of a Low Power and High Speed Hybrid 1-Bit Full Adder for ULSI Circuits” International Journal of Science and Research (IJSR), ISSN (Online): 2319-7064, Volume 5 Issue 9, September 2016.
8. K Mariya Priyadarshini, Dr.R.S.Ernest Ravindran, “Novel Two Fold Edge Activated Memory Cell with Low Power Dissipation and High Speed”, International Journal of Recent Technology and EngineeringVolume 8, Issue 1, May 2019, Pages 1491-1495.
9. K Mariya Priyadarshini, Dr.R.S.Ernest Ravindran, P. Ratna Bhaskar, “A Detailed Scrutiny and Reasoning on VLSI Binary
Adder Circuits and Architectures”International Journal of Innovative Technology and Exploring EngineeringVolume 8, Issue 7, May 2019, Pages 887-895
10. R. S. Ernest Ravindran, K Mariya Priyadarshini, Dangeti Peda Manikya Pavana Teja, Popuri Nikhil Chakravarthy, Peruboyina Dharma Teja, “Design of RAM using Quantum Cellular Automata (QCA) Designer”, International Journal of Scientific and Technology Research, Volume 8, Issue 8, August 2019 ISSN 2277-8616, Pages 1385-1390.
11. D Naveen Sai , Surya Kranth G, Paradhasaradhi D, R.S Ernest Ravindran, Lakshmana Kumar M, K Mariya Priyadarshini, Five Input Multilayer Full Adder by QCA Designer” 3rd International Conference on Advances in Computing and Data Sciences, ICACDS 2019; Ghazibad India, 12 April 2019 through 13 April 2019”
12. R.S. Ernest Ravindran, Mariya Priyadarshini, Kavuri Mahesh, Vanga Krishna Vamsi , Chaitanya Eswar , Bishan Yasaswi,” A Novel 24T Conventional adder vs Low Power Reconstructable Transistor Level Conventional Adder”, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249-8958, Volume-8 Issue-5, June 2019, Pages 398-402.
13. K.Mariya Priyadarshini, Sampad Kumar Panda, R.S. Ernest Ravindran, S Sarvani, P Mohan Vinay, B Suresh Gopi Chand”Performance Analysis of Dual Edge Triggered Memory Cells using Multiple C-Elements” International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8 Issue-4, November 2019.
14. K.Mariya Priyadarshini , Vipul Agarwal , R.S. Ernest Ravindran , T.Hareesh , B.Harsha , G.V. Kalayan “Design of Low-Power, Area Efficient 2-4 and 4-16 Mixed-Logic Line Decoders” Jour of Adv Research in Dynamical & Control Systems, Vol. 11, Special Issue-08, 2019.
15. K.Mariya Priyadarshini, T.P.S. Kumar Kusumanchi, R.S. Ernest Ravindran, E.Naga Lakshmi bhavani, K.Lahari, P.Maheswari “Low Power High Speed Robust SRAM Cells” International Journal of Advanced Science and Technology Vol. 28, No. 20, (2019), pp. 53-62.
16. R. S Ernest Ravindran , K. Mariya Priyadarshini , A. Thanusha sai , P. Shiny, Sk. Sabeena “Design of Finite field Multiplier for Efficient Data Encryption” International Journal of Advanced Science and Technology Vol. 28, No. 20, (2019), pp. 42-52.
17. K. Mariya Priyadarshini , R. S. Ernest Ravindran , M. Atindra Chandra Sekhar , P. J. V. Sai Kalyan , G. Rahul “A High-Speed Precision-Controllable Approximate 16 bit Multiplier” International Journal of Advanced Science and Technology Vol. 28, No. 20, (2019), pp. 31-41
18. K. Mariya Priyadarshini,Vipul Agarwal, R. S Ernest Ravindran, K. Mercy Romitha, Pritika Kanchan, Kurra Harshita“Logical Fault Modelling Algorithm for Stuck-at-fault”, International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8 Issue-5, January 2020.
19. Priyadarshini, K.M., Ernest Ravindran, R.S., Kumar, R.V., ...Sai Bhattar, S.S., Pavan Sri Kalian, T. “Design and implementation of dual edge triggered shift registers for iot applications”, International Journal of Scientific and Technology Research, 2019, 8(10), pp. 3585–3594
20. K Mariya Priyadarshini , R.S Ernest Ravindran , Ipseeta Nanda “A Novel Two Level Edge Activated Carry Save Adder for High Speed Processors” (IJACSA) International Journal of Advance d Computer Science and Applications, Vol. 11, No. 4, May 2020.
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